
module value_a(
    input           clk,
    input           a1,
    input           a2,
    
    output     reg     b1,
    output     reg     b2,
    
    output     reg      c1,
    output     reg     c2,
    
    output    wire      d1,
    output    wire      d2
);

// // // =
// always @(a1)
//     begin
//         b1 = a1;
//         c1 <= a1;
//     end

// <=
always @(posedge clk)
    begin
        b1 = a1;
        c1 = b1;

        b2 <= a2;
        c2 <= b2;
    end

assign d1 = c1;
assign d2 = c2;
    
endmodule 

